ACVI 2016, IEEE Workshop on Architecture Centric Virtual Integration, 5-8 April 2016, Venice, Italy
The communication capabilities of recent embedded systems offer more opportunities for attack to cyber criminals. Moreover, those attacks may compromise the safety of these systems. SysML-Sec is a SysML-based environment for the design of such embedded systems with safety and security features. The paper focuses on the SysML-Sec methodology containing the following stages: assumptions, requirements, attacks,
partitioning, software design and software deployment. Our method is supported by TTool, and offers a press-button approach for formal proof of safety and security. Previous projects and case studies modeled and validated with SysMLSec range from automotive systems, drone systems, information systems (e.g., the analysis of malware targeting banking systems), industrial systems (Analysis of SCADA malware), and more generally, security protocols.
Type:
Conférence
City:
Venice
Date:
2016-04-05
Department:
Sécurité numérique
Eurecom Ref:
4973
Copyright:
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